module rt71_line_buffer_ctrl(
dclk,
rclk,
reset_n,

res,                                //input resolution
in_end_frame,
in_goa_endframe,
in_data_rst_r,  
in_data_rst_f,    

pix_sft_en,
sft_dir,
sft_sel,
data_sft_rgb,
frvs,
brvs,

in_nml_de,
in_nml_rgb,

out_xdio_rt72,
out_sram0_lb1_wr, out_sram1_lb1_wr,             //wen = out_sram?_lb?_wr 
out_sram0_lb2_wr, out_sram1_lb2_wr,

out_sram0_lb1_rd, out_sram1_lb1_rd,             //cen = (out_sram?_lb?_wr|out_sram?_lb?_rd_t)
out_sram0_lb2_rd, out_sram1_lb2_rd,

out_sram0_lb1_addr, out_sram1_lb1_addr,         //addr_insram  (max=1280+11,11bit)
out_sram0_lb2_addr, out_sram1_lb2_addr,    

out_sram0_lb1_wdata, out_sram1_lb1_wdata,       //din 
out_sram0_lb2_wdata, out_sram1_lb2_wdata,

out_clk_sel_sram0,
out_clk_sel_sram1
);

//Din
input dclk;
input rclk;
input reset_n;

input [10:0] res;                                   //flexable, default=1920;                            
input        in_end_frame;
input        in_goa_endframe;
input        in_data_rst_r;                         // gen xdio
input        in_data_rst_f;                                  

input       pix_sft_en;
input       sft_dir;
input [2:0] sft_sel;
input       data_sft_rgb;
input       frvs;
input       brvs;


input        in_nml_de;
input [23:0] in_nml_rgb;

output out_xdio_rt72;
output out_sram0_lb1_wr, out_sram1_lb1_wr;                    //wen = out_sram?_lb?_wr 
output out_sram0_lb2_wr, out_sram1_lb2_wr;

output out_sram0_lb1_rd, out_sram1_lb1_rd;                    //cen = (out_sram?_lb?_wr|out_sram?_lb?_rd)
output out_sram0_lb2_rd, out_sram1_lb2_rd;

output [9:0] out_sram0_lb1_addr, out_sram1_lb1_addr;         //addr (max=961 ,10bit)
output [9:0] out_sram0_lb2_addr, out_sram1_lb2_addr;    

output [23:0] out_sram0_lb1_wdata, out_sram1_lb1_wdata;       //din
output [23:0] out_sram0_lb2_wdata, out_sram1_lb2_wdata;

output out_clk_sel_sram0;
output out_clk_sel_sram1;

//Data delay
reg [23:0] rgb_d1, rgb_d2;           
always @(posedge dclk or negedge reset_n)
begin
 if (!reset_n)
 begin
  rgb_d1 <= 30'd0; 
  rgb_d2 <= 30'd0; 
 end else begin
     rgb_d1 <= in_nml_rgb; 
     rgb_d2 <= rgb_d1; 
     end
end

//DE delay
wire end_frame = (in_end_frame |in_goa_endframe);
reg nml_de_d1, nml_de_d2, nml_de_d3, nml_de_d4;
always @( posedge dclk or negedge reset_n )
begin
  if (!reset_n)
  begin
    nml_de_d1 <= 1'd0;  
    nml_de_d2 <= 1'd0;
    nml_de_d3 <= 1'd0;
    nml_de_d4 <= 1'd0;        
  end else begin
    nml_de_d1 <= in_nml_de;
    nml_de_d2 <= nml_de_d1;
    nml_de_d3 <= nml_de_d2;
    nml_de_d4 <= nml_de_d3;    
  end
end

reg endframe_d1;
always @( posedge rclk or negedge reset_n )
begin
  if (!reset_n)
  endframe_d1 <= 1'd0;
  else
  endframe_d1 <= end_frame;
end


wire endframe_pe = (end_frame & ~endframe_d1);    
wire nml_de_pe  = in_nml_de & (~nml_de_d1);
wire nml_de_ne  = (~in_nml_de) & nml_de_d1;
wire nml_de_ne_d1  = (~nml_de_d1) & nml_de_d2;





//line buffer 1
reg [9:0] wr_half_addr;                              //for lb1 end address
always @( posedge dclk or negedge reset_n )
begin
  if (!reset_n)
  begin
  wr_half_addr <= 10'd0;
  end else if (sft_dir)
      wr_half_addr <= res[10:1];                      //default = 960
      else
      wr_half_addr <= res[10:1] - 10'd1;              //dafault = 959 
end


reg lb1_wen;
reg [9:0] lb1_wr_addr;
always @( posedge dclk or negedge reset_n )
begin
  if (!reset_n)
  begin
  lb1_wr_addr <= 10'd0;
  end else if (endframe_pe)
      lb1_wr_addr <= 10'd0;
           else if (nml_de_pe)
           lb1_wr_addr <= 10'd0;
                else if (lb1_wr_addr == wr_half_addr)      //sft_dir = 0, cnt to 959, sft_dir = 1, cnt to 960,
                lb1_wr_addr <= 10'd0;
                     else if (lb1_wen)
                     lb1_wr_addr <= lb1_wr_addr + 10'd1;
                          else
                          lb1_wr_addr <= 10'd0;
end


//reg lb1_wen; 
always @( posedge dclk or negedge reset_n )
begin
  if (!reset_n)
  begin
  lb1_wen <= 1'd0;
  end else if (nml_de_pe)
      lb1_wen <= 1'd1;
           else if (lb1_wr_addr == wr_half_addr)      //lb1_wr_addr=958 (next clk falling)
           lb1_wen <= 1'd0;
                else
                lb1_wen <= lb1_wen;
end


//line buffer 2
wire wr_de_half = (lb1_wr_addr == (wr_half_addr)) ? 1'd1 : 1'd0;     //half de flag, pulse at lb1_wr_addr = wr_half_addr
wire [9:0] lb2_addr_start = (sft_dir)  ? 10'd1 : 10'd0;                 //for lb2 start address

reg lb2_wen;
reg [9:0] lb2_wr_addr;
always @( posedge dclk or negedge reset_n )
begin
  if (!reset_n)
  begin
  lb2_wr_addr <= 10'd0;
  end else if (endframe_pe)
      lb2_wr_addr <= 10'd0;
           else if (wr_de_half)
           lb2_wr_addr <= lb2_addr_start;
                else if ((lb2_wr_addr == 10'd960) & data_sft_rgb)          //sft_dir=1, lb2_wr_addr end at 960(addr)
                lb2_wr_addr <= 10'd0;
                     else if (lb2_wr_addr == 10'd959 & (~data_sft_rgb))
                     lb2_wr_addr <= 10'd0;                
                          else if (lb2_wen)
                          lb2_wr_addr <= lb2_wr_addr + 10'd1;
                               else
                               lb2_wr_addr <= 10'd0;
end             


//reg lb2_wen;
always @( posedge dclk or negedge reset_n )
begin
  if (!reset_n)
  begin
  lb2_wen <= 1'd0;
  end else if (wr_de_half)
      lb2_wen <= 1'd1;
           else if ((lb2_wr_addr == 10'd960) & data_sft_rgb)         //if data_sft_rgb=1, lb2_wr_addr=960 (next clk falling)
           lb2_wen <= 1'd0;
                else if (lb2_wr_addr == 10'd959 & (~data_sft_rgb))
                lb2_wen <= 1'd0;
                     else
                     lb2_wen <= lb2_wen;
end



// signal to sram

//write line counter 
reg [1:0] wr_line_no;                                //reference nml_de_pe 
always @(posedge dclk or negedge reset_n)
begin
  if (!reset_n)
  begin
    wr_line_no <= 2'd3;
  end else begin
      if( endframe_pe )
         wr_line_no <= 2'd3;
      else if ( nml_de_pe & (wr_line_no == 2'd1)) 
           wr_line_no <= 2'd0; 
           else if ( nml_de_pe ) 
                wr_line_no <= wr_line_no + 2'd1;  
                //else if (nml_de_ne & in_end_frame)    //for glitch in end_frame reset 
                //     wr_line_no <= 2'd3;        
                     else
                        wr_line_no <= wr_line_no;
      end
end


wire sram_wr_flag = nml_de_d1 | nml_de_d3;                  //de_d3??      
wire wr_sram0 = (wr_line_no == 2'd0) & sram_wr_flag; 
wire wr_sram1 = (wr_line_no == 2'd1) & sram_wr_flag; 


//write (wen)
wire out_sram0_lb1_wr = wr_sram0 & lb1_wen;           //1st line wen
wire out_sram0_lb2_wr = wr_sram0 & lb2_wen;

wire out_sram1_lb1_wr = wr_sram1 & lb1_wen;           //2nd line wen
wire out_sram1_lb2_wr = wr_sram1 & lb2_wen;





//write in SRAM

//1st set SRAM
wire [9:0] w_out_sram0_lb1_addr = out_sram0_lb1_wr ? lb1_wr_addr : 10'd0; //(chfb ? lb2_wr_addr : lb1_wr_addr) : 10'd0;     //to do port_rvs in write
wire [9:0] w_out_sram0_lb2_addr = out_sram0_lb2_wr ? lb2_wr_addr : 10'd0; //(chfb ? lb1_wr_addr : lb2_wr_addr) : 10'd0;
reg [23:0] out_sram0_lb1_wdata, out_sram0_lb2_wdata;
always @(posedge dclk or negedge reset_n)
begin
 if (!reset_n)
  begin
   out_sram0_lb1_wdata <= 24'd0;
   out_sram0_lb2_wdata <= 24'd0;
 end else if (out_sram0_lb2_wr | wr_de_half) // & ~chfb)
     begin
     out_sram0_lb1_wdata <= 24'd0;
     out_sram0_lb2_wdata <= in_nml_rgb; 
     end else if (out_sram0_lb1_wr | nml_de_pe) // & ~chfb)
         begin 
         out_sram0_lb1_wdata <= in_nml_rgb;
         out_sram0_lb2_wdata <= 24'd0;  
        //end else if (out_sram0_lb1_wr | nml_de_pe & chfb)           // port_rvs=1, change lb1,lb2
        //    begin
        //    out_sram0_lb1_wdata <= 24'd0;
        //    out_sram0_lb2_wdata <= in_nml_rgb; 
        //    end else if (out_sram0_lb2_wr | wr_de_half & chfb)      // port_rvs=1, change lb1,lb2
        //        begin 
        //        out_sram0_lb1_wdata <= in_nml_rgb;
        //        out_sram0_lb2_wdata <= 24'd0;  
                 end else begin
                     out_sram0_lb1_wdata <= 24'd0;
                     out_sram0_lb2_wdata <= 24'd0;  end
  end
 


//2nd set SRAM
wire [9:0] w_out_sram1_lb1_addr = out_sram1_lb1_wr ? lb1_wr_addr : 10'd0;  //(chfb ? lb2_wr_addr : lb1_wr_addr) : 10'd0;
wire [9:0] w_out_sram1_lb2_addr = out_sram1_lb2_wr ? lb2_wr_addr : 10'd0;  //(chfb ? lb1_wr_addr : lb2_wr_addr) : 10'd0;
reg [23:0] out_sram1_lb1_wdata, out_sram1_lb2_wdata;
always @(posedge dclk or negedge reset_n)
begin
 if (!reset_n)
  begin
   out_sram1_lb1_wdata <= 24'd0;
   out_sram1_lb2_wdata <= 24'd0;
  end else if (out_sram1_lb2_wr | wr_de_half) // & ~chfb)
      begin 
      out_sram1_lb1_wdata <= 24'd0;
      out_sram1_lb2_wdata <= in_nml_rgb; 
      end else if (out_sram1_lb1_wr | nml_de_pe) // & ~chfb)
          begin 
          out_sram1_lb1_wdata <= in_nml_rgb;
          out_sram1_lb2_wdata <= 24'd0;  
         //end else if (out_sram1_lb1_wr | nml_de_pe & chfb)             // port_rvs=1, change lb1,lb2
         //    begin 
         //    out_sram1_lb1_wdata <= 24'd0;
         //    out_sram1_lb2_wdata <= in_nml_rgb; 
         //    end else if (out_sram1_lb2_wr | wr_de_half & chfb)       // port_rvs=1, change lb1,lb2
         //        begin 
         //        out_sram1_lb1_wdata <= in_nml_rgb;
         //        out_sram1_lb2_wdata <= 24'd0;  
                  end else begin
                      out_sram1_lb1_wdata <= 24'd0;
                      out_sram1_lb2_wdata <= 24'd0;  end
  end



  
  
  
  
   
//read out from sram 
//reg xdio_pre_cross;
//always @( posedge dclk or negedge reset_n )
//begin
//  if (!reset_n)
//  xdio_pre_cross <= 1'd0;
//  else if (in_data_rst_r)
//       xdio_pre_cross <= 1'd1;
//       else if (in_data_rst_f)
//            xdio_pre_cross <= 1'd0;
//            else
//            xdio_pre_cross <= xdio_pre_cross;
//end
//
//reg xdio_pre_latch;
//always @( posedge rclk or negedge reset_n )
//begin
//  if (!reset_n)
//  xdio_pre_latch <= 1'd0;
//  else if (xdio_pre_cross)
//       xdio_pre_latch <= 1'd1;
//       else
//       xdio_pre_latch <= 1'd0;
//end
//
//reg xdio;                                                // xdio cross clk domain
//always @( posedge rclk or negedge reset_n )
//begin
//  if (!reset_n)
//  xdio <= 1'd0;
//  else if (xdio_pre_latch)
//       xdio <= 1'd1;
//       else
//       xdio <= 1'd0;
//end

reg in_data_rst_r_d1;
always @( posedge rclk or negedge reset_n )
begin
  if (!reset_n)
  in_data_rst_r_d1 <= 1'd0;
  else 
  in_data_rst_r_d1 <= in_data_rst_r;
end

reg in_data_rst_f_d1;
always @( posedge rclk or negedge reset_n )
begin
  if (!reset_n)
  in_data_rst_f_d1 <= 1'd0;
  else 
  in_data_rst_f_d1 <= in_data_rst_f;
end

wire in_data_rst_r_pe = in_data_rst_r & (~in_data_rst_r_d1);
wire in_data_rst_f_pe = in_data_rst_f & (~in_data_rst_f_d1);

reg xdio;
always @( posedge rclk or negedge reset_n )
begin
  if (!reset_n)
  xdio <= 1'd0;
  else if (in_data_rst_r_pe)
       xdio <= 1'd1;
       else if (in_data_rst_f_pe)
            xdio <= 1'd0;
            else
            xdio <= xdio;
end


wire out_xdio_rt72 = xdio;

reg xdio_d1, xdio_d2;
always @( posedge rclk or negedge reset_n )
begin
  if (!reset_n) 
  begin
  xdio_d1 <= 1'd0;
  xdio_d2 <= 1'd0; 
  end else begin
      xdio_d1 <= xdio;
      xdio_d2 <= xdio_d1; end
end

wire xdio_pe = xdio & (~xdio_d1);
wire xdio_ne = ~xdio & xdio_d1; 
wire xdio_d1_pe = xdio_d1 & (~xdio_d2);

reg xdio_ne_d1;
always @( posedge rclk or negedge reset_n )
begin
  if (!reset_n) 
  xdio_ne_d1 <= 1'd0;
  else
  xdio_ne_d1 <= xdio_ne; 
end

// data_sft_rgb to do pixel shift for read data (dclk domian)
reg [1:0] rd_frame_no;
always @(posedge rclk or negedge reset_n)
begin 
if (!reset_n)
 rd_frame_no <= 2'd3;
else begin 
     if (endframe_pe)
        rd_frame_no <= 2'd3;
     else if (xdio_ne) 
          rd_frame_no <= rd_frame_no + 2'd1;
          else 
          rd_frame_no <= rd_frame_no;
          end
end


reg data_sft_rgb_rd;
always @(posedge rclk or negedge reset_n)
begin 
if (!reset_n)
 data_sft_rgb_rd <= 1'd0;
else if (pix_sft_en == 1'd0)
 data_sft_rgb_rd <= 1'd0; 
else if (xdio_ne_d1) begin
     case ({sft_sel, rd_frame_no})
     //sft_sel=000
     5'b00000: data_sft_rgb_rd <= 1'd0;
     5'b00001: data_sft_rgb_rd <= 1'd1;
     5'b00010: data_sft_rgb_rd <= 1'd0;
     5'b00011: data_sft_rgb_rd <= 1'd1;
     //sft_sel=001
     5'b00100: data_sft_rgb_rd <= 1'd0;
     5'b00101: data_sft_rgb_rd <= 1'd0;
     5'b00110: data_sft_rgb_rd <= 1'd1;
     5'b00111: data_sft_rgb_rd <= 1'd1;
     //sft_sel=010 
     5'b01000: data_sft_rgb_rd <= 1'd0;
     5'b01001: data_sft_rgb_rd <= 1'd1;
     5'b01010: data_sft_rgb_rd <= 1'd1;
     5'b01011: data_sft_rgb_rd <= 1'd0;
     //sft_sel=100
     5'b10000: data_sft_rgb_rd <= 1'd1;
     5'b10001: data_sft_rgb_rd <= 1'd0;
     5'b10010: data_sft_rgb_rd <= 1'd1;
     5'b10011: data_sft_rgb_rd <= 1'd0;
     //sft_sel=101
     5'b10100: data_sft_rgb_rd <= 1'd1;
     5'b10101: data_sft_rgb_rd <= 1'd1;
     5'b10110: data_sft_rgb_rd <= 1'd0;
     5'b10111: data_sft_rgb_rd <= 1'd0;
     //sft_sel=110
     5'b11000: data_sft_rgb_rd <= 1'd1;
     5'b11001: data_sft_rgb_rd <= 1'd0;
     5'b11010: data_sft_rgb_rd <= 1'd0;
     5'b11011: data_sft_rgb_rd <= 1'd1;
     default:  data_sft_rgb_rd <= 1'd0;
     endcase
     end
     else
     data_sft_rgb_rd <= data_sft_rgb_rd;
end





reg rd_line_no;                                   //reference xdio_d1
always @(posedge rclk or negedge reset_n)
begin
  if (!reset_n)
  begin
    rd_line_no <= 1'd1;
  end else if( end_frame )
       rd_line_no <= 1'd1;
           else if ( xdio_ne )
           rd_line_no <= rd_line_no + 2'd1;
                else
                rd_line_no <= rd_line_no;
end

wire rd_sram0 = (rd_line_no == 2'd0); 
wire rd_sram1 = (rd_line_no == 2'd1); 


//ren
reg lb_ren;
reg [9:0] lb_ren_cnt;
always @(posedge rclk or negedge reset_n)
begin
if (!reset_n)
begin
 lb_ren_cnt <= 10'd0;
end else if (endframe_pe)
    lb_ren_cnt <= 10'd0;
         else if (xdio_ne)
         lb_ren_cnt <= 10'd0;
              else if (lb_ren_cnt == 10'd959 & ~data_sft_rgb_rd)            //data_sft_rgb_rd=0, falling at lb_ren_cnt = 959
              lb_ren_cnt <= 10'd0;
                   else if (lb_ren_cnt == 10'd960 & data_sft_rgb_rd)        //data_sft_rgb_rd=1 & pix_sft_en=1 , falling at lb_ren_cnt = 960
                   lb_ren_cnt <= 10'd0;
                        else if (lb_ren)
                        lb_ren_cnt <= lb_ren_cnt + 10'd1;
                        else
                        lb_ren_cnt <= 10'd0;
 end


//reg lb_ren;
always @(posedge rclk or negedge reset_n)
begin
if (!reset_n)
begin
 lb_ren <= 1'd0;
end else if (xdio_ne)
    lb_ren <= 1'd1;
         else if (lb_ren_cnt == 10'd959 & ~data_sft_rgb_rd)                        //data_sft_rgb_rd=0, falling at lb_ren_cnt = 959
         lb_ren <= 1'd0;
              else if (lb_ren_cnt == 10'd960 & data_sft_rgb_rd)                    //data_sft_rgb_rd=1 & pix_sft_en=1 , falling at lb_ren_cnt = 960
              lb_ren <= 1'd0;
                        else
                        lb_ren <= lb_ren;
end



reg lb_ren_d1;
always @(posedge rclk or negedge reset_n)
begin
if (!reset_n)
begin
 lb_ren_d1 <= 1'd0;
end else 
    lb_ren_d1 <= lb_ren;
end


// read (cen)
wire out_sram0_lb1_rd = out_sram0_lb1_wr | (rd_sram0 & lb_ren_d1);        //1st line cen
wire out_sram0_lb2_rd = out_sram0_lb2_wr | (rd_sram0 & lb_ren_d1);       
                                                     
wire out_sram1_lb1_rd = out_sram1_lb1_wr | (rd_sram1 & lb_ren_d1);        //2nd line cen
wire out_sram1_lb2_rd = out_sram1_lb2_wr | (rd_sram1 & lb_ren_d1);       
                                                     



//rd_addr
reg [9:0] lb1_rd_addr_start;
always @(posedge rclk or negedge reset_n)
begin
if (!reset_n)
begin
 lb1_rd_addr_start <= 10'd0;
end else if (frvs & sft_dir) 
    lb1_rd_addr_start <= 10'd960;
         else if (frvs & ~sft_dir)
         lb1_rd_addr_start <= 10'd959;
              else
              lb1_rd_addr_start <= 10'd0;
end


reg [9:0] lb2_rd_addr_start;
always @(posedge rclk or negedge reset_n)
begin
if (!reset_n)
begin
 lb2_rd_addr_start <= 10'd0; 
end else if (brvs & sft_dir) 
    lb2_rd_addr_start <= 10'd960;
         else if (brvs & ~sft_dir)
         lb2_rd_addr_start <= 10'd959;
              else if (frvs & sft_dir)
              lb2_rd_addr_start <= 10'd1;
                   else
                   lb2_rd_addr_start <= 10'd0; 
end


reg [9:0] lb1_rd_addr;
always @(posedge rclk or negedge reset_n)
begin
if (!reset_n)
begin
 lb1_rd_addr <= 10'd0;
end else if (endframe_pe)
    lb1_rd_addr <= 10'd0;  
         else if (xdio_ne)
         lb1_rd_addr <= lb1_rd_addr_start;
              else if (frvs & lb_ren)    //in lb_ren area, lb1_rd_addr + or -
              lb1_rd_addr <= lb1_rd_addr - 10'd1; 
                   else if (lb_ren)
                   lb1_rd_addr <= lb1_rd_addr + 10'd1; 
                        else
                        lb1_rd_addr <= 10'd0;
end


reg [9:0] lb2_rd_addr;
always @(posedge rclk or negedge reset_n)
begin
if (!reset_n)
begin
 lb2_rd_addr <= 10'd0;
end else if (endframe_pe)
    lb2_rd_addr <= 10'd0; 
         else if (xdio_ne)
         lb2_rd_addr <= lb2_rd_addr_start;
              else if (brvs & lb_ren)                   //in lb_ren area, lb2_rd_addr + or -
              lb2_rd_addr <= lb2_rd_addr - 10'd1;
                   else if (lb_ren)
                   lb2_rd_addr <= lb2_rd_addr + 10'd1; 
                        else
                        lb2_rd_addr <= 10'd0;
end




//1st set SRAM 
reg [9:0] r_out_sram0_lb1_addr, r_out_sram0_lb2_addr;
always @(posedge rclk or negedge reset_n)
begin
if (!reset_n)
begin
  r_out_sram0_lb1_addr <= 10'd0;
  r_out_sram0_lb2_addr <= 10'd0;
end else if (rd_sram0 & lb_ren) begin
    r_out_sram0_lb1_addr <= lb1_rd_addr;
    r_out_sram0_lb2_addr <= lb2_rd_addr; end
         else begin
         r_out_sram0_lb1_addr <= 10'd0;
         r_out_sram0_lb2_addr <= 10'd0;  end
end


//2nd set SRAM 
reg [9:0] r_out_sram1_lb1_addr, r_out_sram1_lb2_addr;
always @(posedge rclk or negedge reset_n)
begin
if (!reset_n)
begin
  r_out_sram1_lb1_addr <= 10'd0;
  r_out_sram1_lb2_addr <= 10'd0;
end else if (rd_sram1 & lb_ren) begin
    r_out_sram1_lb1_addr <= lb1_rd_addr;
    r_out_sram1_lb2_addr <= lb2_rd_addr; end
         else begin
         r_out_sram1_lb1_addr <= 10'd0;
         r_out_sram1_lb2_addr <= 10'd0; end
end





// address to sram
wire [9:0] out_sram0_lb1_addr, out_sram1_lb1_addr;
assign out_sram0_lb1_addr = (out_sram0_lb1_wr) ? w_out_sram0_lb1_addr : r_out_sram0_lb1_addr;
assign out_sram1_lb1_addr = (out_sram1_lb1_wr) ? w_out_sram1_lb1_addr : r_out_sram1_lb1_addr;

wire [9:0] out_sram0_lb2_addr, out_sram1_lb2_addr;
assign out_sram0_lb2_addr = (out_sram0_lb2_wr) ? w_out_sram0_lb2_addr : r_out_sram0_lb2_addr;
assign out_sram1_lb2_addr = (out_sram1_lb2_wr) ? w_out_sram1_lb2_addr : r_out_sram1_lb2_addr;


//clk_sel to clk_gen
reg out_sram0_lb1_wr_d1, out_sram1_lb1_wr_d1,             //wen = out_sram?_lb?_wr 
    out_sram0_lb2_wr_d1, out_sram1_lb2_wr_d1,
    out_sram0_lb1_wr_d2, out_sram1_lb1_wr_d2,
    out_sram0_lb2_wr_d2, out_sram1_lb2_wr_d2;
always @(posedge dclk or negedge reset_n)
begin
if (!reset_n) begin
  out_sram0_lb1_wr_d1 <= 1'd0;
  out_sram0_lb2_wr_d1 <= 1'd0;
  out_sram0_lb1_wr_d2 <= 1'd0;
  out_sram0_lb2_wr_d2 <= 1'd0;
  out_sram1_lb1_wr_d1 <= 1'd0;
  out_sram1_lb2_wr_d1 <= 1'd0; 
  out_sram1_lb1_wr_d2 <= 1'd0; 
  out_sram1_lb2_wr_d2 <= 1'd0; end  
else begin
  out_sram0_lb1_wr_d1 <= out_sram0_lb1_wr;
  out_sram0_lb2_wr_d1 <= out_sram0_lb2_wr;
  out_sram1_lb1_wr_d1 <= out_sram1_lb1_wr;
  out_sram1_lb2_wr_d1 <= out_sram1_lb2_wr; 
  out_sram0_lb1_wr_d2 <= out_sram0_lb1_wr_d1;
  out_sram0_lb2_wr_d2 <= out_sram0_lb2_wr_d1;
  out_sram1_lb1_wr_d2 <= out_sram1_lb1_wr_d1; 
  out_sram1_lb2_wr_d2 <= out_sram1_lb2_wr_d1; end
end


wire out_clk_sel_sram0 = ((out_sram0_lb1_wr | out_sram0_lb1_wr_d2) | (out_sram0_lb2_wr | out_sram0_lb2_wr_d2)) ? 1'd1 : 1'd0;
wire out_clk_sel_sram1 = ((out_sram1_lb1_wr | out_sram1_lb1_wr_d2) | (out_sram1_lb2_wr | out_sram1_lb2_wr_d2)) ? 1'd1 : 1'd0;



endmodule  
